
Pentium III
Product brand
UnclaimedIntel's sixth-generation P6-based family of 32-bit desktop and mobile x86 microprocessors.
Last updated August 26, 2026
Overview
Pentium III was a family of 32-bit x86 microprocessors marketed by Intel from 1999 through the middle of the 2000s. It extended the company's P6 microarchitecture, which had first appeared in the Pentium Pro and had subsequently powered the Pentium II. The principal architectural addition was Streaming SIMD Extensions, or SSE, an instruction set intended to accelerate vectorized floating-point, multimedia, imaging, and other parallel workloads. Pentium III processors also introduced a controversial processor serial-number feature on early models, allowing software to read a unique identifier embedded in the chip. Intel later omitted the feature from Tualatin-based parts and subsequent processor generations after privacy concerns and customer resistance. The first Pentium III processors used the Katmai core and were introduced on February 28, 1999, at 450 MHz and 500 MHz. Katmai was closely related to the Pentium II's Deschutes core and used a 250 nm manufacturing process. Later Katmai models reached 600 MHz and introduced variants with a 133 MT/s front-side bus. The design retained an external half-speed L2 cache implemented in the cartridge package, so its performance gains over comparable Pentium II processors were generally incremental except in software optimized for SSE. Intel's larger second revision, Coppermine, arrived in October 1999. It moved to a 180 nm process and integrated 256 KB of full-speed on-die L2 cache, which Intel called Advanced Transfer Cache. This change substantially reduced cache latency and improved performance, efficiency, and scalability. Coppermine parts were sold in both 100 MT/s and 133 MT/s front-side-bus versions and eventually reached 1 GHz. They appeared in Slot 1 and Socket 370 packages, with later models using an integrated heat spreader. A 1.13 GHz Coppermine released in 2000 was recalled after independent testing found instability; a revised stepping was released later. The final major revision was Tualatin, a 130 nm shrink introduced in 2001 and extended into early 2002. Tualatin models ranged from approximately 1 GHz to 1.4 GHz and incorporated improved data-prefetch behavior. Versions with 256 KB of L2 cache were sold as mainstream Pentium III processors, while 512 KB versions carried the Pentium III-S designation and targeted low-power servers and workstations. Tualatin required different signaling and power-management support, limiting compatibility with many earlier Socket 370 motherboards. Its efficient P6 design nevertheless performed strongly in some workloads against early Pentium 4 processors based on Intel's power-hungry NetBurst architecture. Pentium III coexisted with related Intel brands. Celeron covered lower-cost derivatives, while Xeon served server and workstation markets. Pentium 4 eventually became Intel's principal desktop successor, but Pentium III continued to be produced after Pentium 4's introduction, particularly in mobile systems. The Tualatin design also formed the technical foundation for the Pentium III-M mobile line and influenced the later Pentium M and energy-efficient Core architecture. Desktop production ended in April 2004, while mobile production continued until May 2007. The brand is therefore historically significant as the mature phase of Intel's P6 family and as an important bridge between the Pentium II era and the later Core family.
History
Pentium III developed from Intel's P6 architecture and succeeded the Pentium II as the company's mainstream 32-bit desktop and mobile processor family. Its launch on February 28, 1999 introduced SSE, which gave software developers new instructions for processing multiple floating-point values in parallel. The initial Katmai core was architecturally close to Deschutes, the Pentium II core, but added SSE execution resources, an improved L1 cache controller, and other refinements. It was manufactured on a 250 nm process and initially used a Slot 1 cartridge. Early processors operated at 450 MHz and 500 MHz, with later 533, 550, and 600 MHz versions and variants supporting a faster 133 MT/s front-side bus. The brand attracted controversy because early processors included a processor serial number that could be read by software. Intel presented the identifier as useful for asset management and security, but privacy advocates and customers objected to the possibility of remote identification and tracking. The company provided mechanisms to disable the feature and later removed it from Tualatin and newer designs. Coppermine, the second major core, launched in October 1999. Its 180 nm process and 256 KB of integrated full-speed L2 cache represented a more substantial performance improvement than Katmai. Intel marketed the cache as Advanced Transfer Cache. Coppermine was offered across a wide range of clock speeds, from 500 MHz to 1 GHz and beyond, with both 100 and 133 MT/s bus variants. Packaging evolved from Slot 1 cartridges to Socket 370 FC-PGA and FC-PGA2 packages. The transition created motherboard and cooling-compatibility issues, especially because early socketed chips had exposed dies that could be damaged by improperly mounted heatsinks. An early 1.13 GHz Coppermine became one of the family's most public product problems. Independent hardware testing reported crashes and instability under demanding conditions, and Intel withdrew the processor. The company subsequently revised the design and released corrected 1.1 GHz and 1.13 GHz models using a later stepping. The episode demonstrated the difficulty of pushing the Coppermine architecture beyond its validated frequency range. Coppermine T served as an intermediate revision with signaling changes intended to bridge older Coppermine-compatible platforms and newer Tualatin support. Tualatin itself was Intel's 130 nm refinement of the design and appeared in 2001 and early 2002 at speeds up to 1.4 GHz. It added data-prefetch logic and was sold with either 256 KB or 512 KB of L2 cache. The 512 KB version, Pentium III-S, was aimed principally at servers and workstations and supported symmetric multiprocessing within the Tualatin family. Tualatin's lower-voltage signaling and revised voltage requirements meant that many older motherboards could not run it, despite the continued use of the Socket 370 designation. Pentium III remained relevant after Pentium 4 arrived in late 2000. The P6 design often offered competitive performance per clock and lower power consumption than early Willamette Pentium 4 processors, making it particularly useful in notebooks. The Tualatin core became the basis for Pentium III-M, Intel's leading mobile processor line for a period when Pentium 4's power consumption limited its notebook suitability. Ideas from this efficient P6-derived mobile lineage later influenced Pentium M and Intel's Core microarchitecture. Intel ended desktop Pentium III production in April 2004 and mobile production in May 2007.
- 2007
Mobile line discontinued
[1]The remaining mobile Pentium III products were discontinued in May.
- 2004
Desktop line discontinued
[1]Intel ended desktop Pentium III production in April.
- 2001
Tualatin enters the market
[1]The 130 nm Tualatin core extended the family to higher frequencies and enabled Pentium III-S and Pentium III-M derivatives.
- 2000
1.13 GHz Coppermine withdrawn
[1]Intel recalled an early 1.13 GHz model after instability was reported in testing.
- 1999
Pentium III launches with Katmai
[1]Intel introduced the first Pentium III processors at 450 MHz and 500 MHz, adding SSE to the P6 family.
- 1999
133 MT/s bus variants arrive
[1]Later Katmai models added a faster front-side bus and received model suffixes distinguishing them from 100 MT/s versions.
- 1999
Coppermine revision launches
[1]The 180 nm Coppermine core introduced a 256 KB full-speed on-die L2 cache and later scaled to 1 GHz and beyond.
Products and positioning
Mainstream desktop and mobile processor family emphasizing incremental P6 performance improvements, SSE support, and later strong performance per watt.
Desktop microprocessor core · 1999
Katmai
The first Pentium III core, Katmai was a 250 nm development of the Pentium II's Deschutes architecture. It added SSE, execution resources, and a refined L1 cache controller while retaining a cartridge-based external L2 cache arrangement. Models ranged from 450 MHz to 600 MHz and used Slot 1 packaging, with later variants supporting a 133 MT/s front-side bus.
Desktop and mobile microprocessor core · 1999
Coppermine
Coppermine was a 180 nm redesign with 256 KB of integrated, full-speed L2 cache. Its lower cache latency and improved internal buffering produced a larger performance gain than the initial Katmai revision. It was sold in Slot 1 and Socket 370 packages, with 100 and 133 MT/s bus versions and clock speeds reaching at least 1 GHz.
Desktop microprocessor revision · 2001
Coppermine-T
Coppermine-T was an intermediate revision designed to support lower-voltage system signaling associated with Tualatin while retaining compatibility with selected earlier platforms. It helped bridge the transition between mainstream Coppermine systems and newer Socket 370 boards.
Desktop and mobile microprocessor core · 2001
Tualatin
Tualatin was a 130 nm refinement of the P6 design. It added data-prefetch logic, reached clock speeds from approximately 1 GHz to 1.4 GHz, and required revised signaling and power support that limited compatibility with many earlier motherboards. Tualatin was also the foundation for the Pentium III-M mobile processor.
Server and workstation processor · 2001
Pentium III-S
Pentium III-S processors used Tualatin silicon with 512 KB of L2 cache. They were intended primarily for low-power servers and workstations and supported symmetric multiprocessing within the Tualatin product family.
Mobile processor · 2001
Pentium III-M
Pentium III-M was the mobile extension of the Tualatin design. It emphasized a balance between notebook performance and power consumption and served as Intel's principal mobile processor family for a period when Pentium 4 was less suitable for portable computers.
Controversies
1999
Processor serial number privacy controversy
Early Pentium III processors included a software-readable processor serial number. Privacy advocates and customers criticized the feature because it could potentially support identification or tracking. Intel offered a way to disable it and subsequently omitted the feature from Tualatin and later processors.
Brand decisions
2001
Introduce the Tualatin process shrinkGeneration changeBackground
Intel sought higher frequencies and improved efficiency while transitioning the P6 family to a 130 nm manufacturing process.
Action taken
Intel introduced Tualatin processors with revised signaling, data-prefetch logic, and variants with up to 512 KB of L2 cache.
Aftermath
Tualatin extended Pentium III's useful life in desktops, servers, and notebooks and provided the technical basis for Pentium III-M and later Pentium M development.
2001
Retain Pentium III for mobile computingStrategyBackground
The early Pentium 4 consumed substantially more power, limiting its suitability for many notebook designs.
Action taken
Intel continued developing and selling mobile Pentium III-M products based on the efficient Tualatin lineage.
Aftermath
The P6-derived mobile approach remained important until Intel's later Pentium M and Core families displaced it.
2000
Withdraw the early 1.13 GHz CoppermineOtherBackground
Independent testing found instability in an early 1.13 GHz Coppermine model under certain operating conditions.
Action taken
Intel recalled or withdrew the affected processor and later prepared a revised stepping.
Aftermath
Corrected 1.1 GHz and 1.13 GHz versions appeared in 2001 after additional validation and silicon changes.
1999
Add SSE to the mainstream P6 processor lineProduct launchBackground
Intel needed to extend the Pentium II platform while improving support for multimedia, floating-point, and parallel workloads.
Action taken
The company launched Pentium III with Streaming SIMD Extensions and related execution hardware.
Aftermath
SSE became an important part of Intel's x86 instruction-set strategy and was retained in later processor generations.
- AMD — AMD's competing Athlon family generally remained competitive in conventional and floating-point workloads, while Pentium III could benefit from software optimized for SSE.
1999
Move to the Coppermine coreGeneration changeBackground
The initial Katmai design retained an external L2 cache arrangement inherited from Pentium II and offered limited performance gains over its predecessor.
Action taken
Intel introduced a 180 nm core with 256 KB of full-speed on-die L2 cache and improved internal buffering.
Aftermath
Coppermine delivered a more substantial performance improvement and enabled Pentium III products to scale toward and beyond 1 GHz.
- AMD — AMD continued competing with Athlon processors, which could achieve higher clock speeds and remained strong in some floating-point workloads.
Recent events
- 2007
Pentium III mobile production ends[1]
Other
The remaining mobile Pentium III products were discontinued in May 2007.
- 2004
Pentium III desktop production ends[1]
Other
Intel discontinued desktop Pentium III production in April 2004, although mobile products remained available for several more years.
- 2001
Intel releases Tualatin-based Pentium III processors[1]
Product launch · Product generation
The Tualatin revision used a 130 nm process and extended the Pentium III line to higher clock speeds, including Pentium III-S server-oriented models.
- 2000
Intel recalls an unstable 1.13 GHz Pentium III[1]
Recall · Other
Independent testing identified operational instability in an early 1.13 GHz Coppermine model. Intel withdrew the processor and later returned with revised silicon.
- 1999
Intel launches the Pentium III processor[1]
Product launch · Product generation
Intel introduced the Pentium III family with Katmai-based processors, adding SSE to its mainstream desktop processor line.
- 1999
Intel introduces Coppermine Pentium III processors[1]
Product launch · Product generation
The Coppermine revision moved to a 180 nm process and integrated a faster on-die L2 cache, improving the performance of the P6 design.
Sources1 sources
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