lowRISC

lowRISC is a UK not-for-profit company headquartered in Cambridge that develops, maintains, and stewards open-source silicon designs and related engineering tools. Its work is centered on collaborative hardware development, particularly around the RISC-V instruction-set architecture, and is intended to make advanced chip design more accessible, inspectable, reusable, and adaptable. The organization emerged from the University of Cambridge Computer Laboratory in 2014. Its founding objective was to create a fully open-source system-on-chip design and an inexpensive development board. Rather than operating primarily as a conventional chip vendor, lowRISC functions as an engineering, governance, and ecosystem organization. It works with universities, technology companies, semiconductor participants, and open-source contributors to produce designs that can be studied, modified, verified, and manufactured by other parties. A major early undertaking was a prototype 64-bit RISC-V system-on-chip design capable of running Linux. A preview of the source code appeared in 2015, and later development added capabilities including tagged-memory support and small processor cores dedicated to input/output tasks. Version 0.6 was released in 2018 for experimentation on field-programmable-gate-array hardware. The project demonstrated how an open hardware organization could combine a processor architecture, a system design, and associated software into a reusable platform. lowRISC has also contributed to the software side of the RISC-V ecosystem. It initiated and led upstreaming work for the RISC-V backend in the LLVM compiler infrastructure, with Alex Bradbury identified as a code owner. This activity reflects the organization's broader scope: its output is not limited to physical chip descriptions, but also includes compilers, verification infrastructure, development tooling, and the engineering practices needed to support open silicon. The Ibex CPU core is one of lowRISC's principal technical assets. Ibex is an open-source, 32-bit, in-order RISC-V processor core intended for embedded applications. Its development began in 2015 under the names Zero-riscy and Micro-riscy within the PULP platform associated with ETH Zurich and the University of Bologna. lowRISC took over development in December 2018. The core has been taped out multiple times and is used in the OpenTitan security-focused chip platform. Since 2018, lowRISC has emphasized collaborative engineering with partner organizations. Its most prominent current responsibility is stewardship of OpenTitan, described as the first open-source silicon root-of-trust project. OpenTitan is designed for integration into servers, storage systems, peripherals, and other hardware requiring a hardware-based security foundation. The project is developed collaboratively with organizations including Google, ETH Zurich, Nuvoton, G+D Mobile Security, Seagate, and Western Digital. Its source code is published on GitHub under the permissive Apache 2.0 license. lowRISC also became a founding member of the RISC-V Foundation in 2015, an organization now known as RISC-V International. Through its projects and governance role, lowRISC occupies a position between open-source software communities, academic research, semiconductor engineering, and commercial hardware development. Its practical value lies in providing reusable designs and trusted collaborative processes rather than selling a branded mass-market device. The organization remains active, with its principal public identity associated with open silicon, RISC-V engineering, Ibex, and OpenTitan.

lowRISC was established in 2014 as a spinout from the University of Cambridge Computer Laboratory by Alex Bradbury, Robert Mullins, and Gavin Ferris. The initial ambition was to develop a fully open-source system-on-chip and an affordable development board, addressing the cost, opacity, and licensing restrictions that often affect conventional chip development. In 2015, the organization published a preview of an open 64-bit RISC-V system-on-chip design capable of running Linux and became one of the founding members of the RISC-V Foundation, now called RISC-V International. The SoC project subsequently evolved with features such as tagged-memory support and small auxiliary processor cores for input/output work. Its 0.6 release, issued in November 2018, could be tested on FPGA hardware. lowRISC's activities expanded beyond complete SoC designs. It supported the open-source RISC-V software ecosystem by initiating and leading upstream work for the RISC-V backend in LLVM. The organization also became involved in the development of the Ibex embedded processor core. Ibex originated in 2015 under the names Zero-riscy and Micro-riscy within the PULP platform associated with ETH Zurich and the University of Bologna. In December 2018, lowRISC assumed responsibility for its development. Ibex is a 32-bit, in-order RISC-V core and has been taped out multiple times. From 2018 onward, lowRISC increasingly focused on collaborative engineering with external partners. This model culminated in the 2019 announcement of OpenTitan, an open-source silicon root-of-trust project stewarded by lowRISC. OpenTitan is intended to provide a reusable security foundation for servers, storage products, peripherals, and other hardware. Its contributors include Google, ETH Zurich, Nuvoton, G+D Mobile Security, Seagate, and Western Digital. The project's code is available under the Apache 2.0 license, supporting inspection and reuse by the wider hardware community. Today, lowRISC is best understood as a not-for-profit open-silicon organization rather than a consumer-facing semiconductor brand. Its activities combine processor-core engineering, SoC design, security hardware, software-toolchain work, project governance, and community coordination. The organization is headquartered in Cambridge and continues to be associated with RISC-V-based open hardware and with stewardship of OpenTitan.

• 2019

  OpenTitan is announced

  [1]LowRISCen.wikipedia.org

  lowRISC announces the OpenTitan open-source silicon root-of-trust project, developed with industry and academic partners.

• 2018

  Ibex development moves to lowRISC

  [1]LowRISCen.wikipedia.org

  lowRISC takes over development of the open-source embedded RISC-V core from its earlier ETH Zurich and University of Bologna development context.

• 2018

  Prototype SoC version 0.6

  [1]LowRISCen.wikipedia.org

  The latest cited version of the prototype 64-bit SoC design, version 0.6, becomes available for FPGA experimentation.

• 2015

  RISC-V ecosystem participation begins

  [1]LowRISCen.wikipedia.org

  lowRISC becomes a founding member of the RISC-V Foundation and releases an early preview of its open 64-bit Linux-capable SoC design.

• 2015

  Ibex predecessor development starts

  [1]LowRISCen.wikipedia.org

  The processor core later known as Ibex begins development as Zero-riscy and Micro-riscy within the PULP platform.

• 2014

  lowRISC is established

  [1]LowRISCen.wikipedia.org

  Alex Bradbury, Robert Mullins, and Gavin Ferris spin lowRISC out of the University of Cambridge Computer Laboratory to pursue open-source SoC and development-board designs.

Collaborative open-source silicon engineering and infrastructure for the RISC-V ecosystem.

• Open-source silicon security platform · 2019

  OpenTitan

  OpenTitan is an open-source silicon root-of-trust project stewarded by lowRISC. It is designed as a hardware security foundation that can be integrated into data-center servers, storage devices, peripherals, and other systems. The project is collaboratively developed by lowRISC and partners including Google, ETH Zurich, Nuvoton, G+D Mobile Security, Seagate, and Western Digital. Its source code is distributed under the permissive Apache 2.0 license. The platform incorporates the Ibex processor core.

• 32-bit RISC-V CPU core · 2015

  Ibex

  Ibex is an open-source, 32-bit, in-order RISC-V processor core intended primarily for embedded systems and security-oriented silicon. It began within the PULP platform under the names Zero-riscy and Micro-riscy, with development associated with ETH Zurich and the University of Bologna. lowRISC took over its development in December 2018. The core has been taped out multiple times and is used within the OpenTitan chip design.

• Open-source system-on-chip design · 2015

  Prototype 64-bit RISC-V SoC

  The prototype 64-bit SoC is an open-source, Linux-capable RISC-V system design developed by lowRISC. An initial source-code preview was released in 2015. Later versions added functions including tagged-memory support and small auxiliary processor cores dedicated to input/output tasks. The cited version 0.6 can be downloaded and tested on FPGA hardware, making the design useful for experimentation and research into open processor systems.

• Compiler infrastructure

  RISC-V LLVM backend

  lowRISC initiated and led upstreaming work for the RISC-V backend in LLVM, helping connect the open instruction-set architecture with a widely used compiler infrastructure. Alex Bradbury is identified as a code owner. This is a software-toolchain contribution rather than a physical product, and it supports compilation for RISC-V-based systems.

• 2019

  OpenTitan project launchProduct launch

  Background

  Hardware security systems often depend on proprietary silicon roots of trust, while open-source hardware projects seek designs that can be inspected and reused.

  Action taken

  lowRISC announced and assumed stewardship of OpenTitan, an open-source silicon root-of-trust project developed with multiple technology and academic partners.

  Aftermath

  OpenTitan became lowRISC's most prominent collaborative project and incorporated the Ibex processor core.

  Source

• 2018

  Shift toward collaborative engineeringStrategy

  Background

  From 2018, lowRISC increasingly focused on collaborative engineering with partner organizations rather than only developing an internal prototype SoC.

  Action taken

  The organization expanded its stewardship, engineering, and ecosystem role, including responsibility for the Ibex project and subsequent OpenTitan collaboration.

  Aftermath

  This direction led to lowRISC's central role in OpenTitan and strengthened its position as an open-silicon project steward.

  Source

• 2019-11-06

  Google announces the OpenTitan open-source chip project[2]谷歌宣布推出OpenTitan开源芯片项目news.qq.com

  Reported: 2019-11-06

  Google announced the OpenTitan project, an open-source hardware initiative for a chip architecture based on the concept of a hardware root of trust.

1. 1LowRISCen.wikipedia.org
2. 2谷歌宣布推出OpenTitan开源芯片项目news.qq.com