Aldec
Aldec is a privately owned electronic design automation company providing software and hardware for FPGA and ASIC design, simulation, verification, emulation, and prototyping.
Last updated August 25, 2026
AI crawler reads
No AI crawler has read this profile since Oct 28, 2026.
Overview
Aldec is a United States electronic design automation company whose products support the creation, simulation, verification, emulation, and prototyping of digital hardware. Founded in 1984 by Dr. Stanley M. Hyduke, the company began with gate-level simulation software for schematic-based digital design and subsequently shifted toward graphical and hardware-description-language-centered development as FPGA and ASIC engineering practices evolved. Aldec’s portfolio is centered on tools used by hardware engineers rather than general-purpose software users. Active-HDL is an integrated FPGA development environment combining schematic and text-based design entry, mixed-language HDL simulation, debugging, and connections to synthesis and implementation tools. Riviera-PRO is positioned for more demanding ASIC and large-FPGA verification work, with capabilities associated with assertion-based verification, functional coverage, verification methodologies, and hardware acceleration. Other software products address linting and design-rule checking, clock-domain-crossing analysis, requirements traceability, and reusable intellectual-property validation. The company also supplies hardware-oriented solutions. Its HES family has been used for simulation acceleration, emulation, hardware/software co-simulation, and ASIC prototyping. The TySOM line consists of embedded-development boards and related expansion products based on SoC FPGA technology. Aldec has additionally offered specialized systems for radiation-hardened FPGA prototyping and DO-254-oriented FPGA verification, reflecting applications in embedded, industrial, aerospace, and other safety- or reliability-sensitive engineering environments. Aldec’s history tracks several important changes in digital-design methodology. Its early simulator products were associated with schematic-entry tools, while Active-CAD introduced a Windows-based design and simulation suite in the early 1990s. The company’s work with Xilinx led to a vendor-specific distribution of Active-CAD under the Foundation name. The later introduction of Active-VHDL, followed by Verilog support and the adoption of the Active-HDL name, marked a broader move toward HDL-based design. During the 2000s and 2010s, Aldec expanded into cross-platform simulation, assertion-based verification, linting, requirements management, emulation, SoC/ASIC prototyping, and embedded development. Aldec also participates in industry-standardization activity through organizations including Accellera and the IEEE Standards Association. Its tools have supported standards and methodologies associated with VHDL, SystemVerilog, SystemC, OpenVera, PSL, OVM, UVM, and VMM. The company has supplied simulation technology for integration into other EDA products and has produced vendor-specific or bundled versions of tools for FPGA ecosystems, including offerings associated with Lattice. Aldec remains a privately held specialist supplier serving FPGA, ASIC, embedded-system, and digital-verification engineering markets.
History
Aldec was founded in 1984 by Dr. Stanley M. Hyduke. Its first product, released in 1985, was SUSIE, an MS-DOS gate-level simulator. Early versions were used alongside schematic-entry products, including tools associated with OrCAD. As graphical Windows-based engineering became more important, Aldec ported its simulator to Windows and added schematic-entry and design-management functions. The resulting Active-CAD suite was released in 1992. A notable feature was the ability to transfer schematic changes directly into simulation, allowing engineers to test modified digital logic with less manual intervention. Some lower-end versions were marketed for a period under the Susie-CAD name. In 1996, Aldec entered an agreement with Xilinx that permitted a Xilinx-specific edition of Active-CAD to be distributed under the Foundation brand. The company then moved more decisively from netlist and schematic-centered design toward hardware description languages. Active-VHDL appeared in 1997. After Verilog support was added, the product was renamed Active-HDL, which became Aldec’s principal integrated FPGA design environment. In 2000, Aldec released a high-performance HDL simulator that ran on Windows, Solaris, and Linux. The following year it added hardware to its portfolio through the HES, or Hardware Embedded Simulation, platform. HES was intended to accelerate HDL simulation and support incremental prototyping. Riviera-PRO was introduced in 2003 as a higher-end simulator for complex FPGA and ASIC designs. Its verification capabilities included assertion-based approaches using OpenVera, PSL, and SystemVerilog. SystemC and additional SystemVerilog support followed in 2004, while MATLAB and Simulink interfaces were added in 2005. In 2006, Riviera-PRO supported the Open IP Encryption Initiative associated with Synplicity. Aldec expanded its verification-analysis tools during the next decade. In 2007 it released an advanced configurable lint tool responding to demand from Verilog users. ALINT, a design-rule checker based on rules associated with the Japanese STARC consortium, followed in 2008. Support for VHDL IEEE 1076-2008 was added in 2010. The company also reported support for UVM 1.0, OVM 2.1.2, and VMM 1.1.1a in 2011, together with a 4 MHz design emulator. In 2012, HES-7 marked a further move into SoC and ASIC prototyping, and Aldec jointly launched work related to OSVVM and VHDL verification. The portfolio broadened beyond simulation and linting with Spec-TRACER, released in 2013 for requirements capture, management, traceability, and reporting in FPGA and ASIC projects. ALINT-PRO followed in 2015 with combined linting and clock-domain-crossing verification. In 2016, Aldec introduced the TySOM line of embedded-development boards and FMC daughter cards using Xilinx Zynq-7000 SoC FPGA technology. The company later reported support for VHDL IEEE 1076-2019 in 2020. Aldec’s hardware products have included HES-7 ASIC prototyping systems, radiation-hardened FPGA prototyping solutions using Microsemi RTAX and RTSX devices, and a DO-254 Compliance Test System for FPGA verification in aerospace-oriented contexts. Its TySOM products target embedded development scenarios such as Internet of Things systems, advanced driver-assistance systems, and industrial machine vision. Aldec has also supplied an HDL simulation engine for integration into other EDA products and offered vendor-specific editions or bundles, including FPGA-oriented versions associated with Lattice. The company participates in standards work through Accellera and the IEEE Standards Association, particularly in areas involving VHDL and SystemVerilog. Aldec is headquartered in Henderson, Nevada, and remains privately owned.
- 2020
VHDL-2019 support reported
[1]Aldec tools add support for IEEE 1076-2019.
- 2016
TySOM product line introduced
[1]Aldec launches embedded-development hardware based on SoC FPGA technology.
- 2013
Spec-TRACER released
[1]Aldec adds requirements lifecycle management and traceability for FPGA and ASIC projects.
- 2012
HES-7 enters ASIC prototyping
[1]The HES-7 product expands Aldec’s hardware-based SoC and ASIC prototyping capabilities.
- 2008
ALINT released
[1]Aldec introduces configurable design-rule checking and linting.
- 2003
Riviera-PRO released
[1]Aldec launches a high-end HDL simulation and verification environment.
- 2001
HES platform added
[1]Aldec enters hardware-assisted simulation and prototyping.
- 1997
Active-VHDL launches
[1]The company introduces an HDL-focused product that later becomes Active-HDL after Verilog support is added.
- 1992
Active-CAD introduced
[1]A Windows-based suite combines schematic entry, design management, and simulation.
- 1985
SUSIE simulator released
[1]Aldec launches its first product, an MS-DOS gate-level simulator.
Products and positioning
A specialist electronic design automation provider for FPGA, ASIC, embedded-system, and digital-hardware design verification workflows.
FPGA design and simulation environment · 1997
Active-HDL
Active-HDL is Aldec’s integrated FPGA development environment. It combines text-based and graphical design entry with HDL simulation, debugging, project management, and links to synthesis and implementation tools. The environment supports mixed-language projects involving VHDL, Verilog, EDIF, SystemC, and SystemVerilog, as well as assertion-based verification using languages and methodologies such as OpenVera, PSL, and SystemVerilog Assertions. Vendor-specific editions have also been offered.
HDL simulation and verification software · 2003
Riviera-PRO
Riviera-PRO is Aldec’s higher-end HDL simulator for ASIC and large-FPGA projects. It extends core simulation with advanced verification functions including assertions, functional coverage, linting, and support for verification methodologies such as OVM and UVM. The product has been available for Windows and Linux environments and is intended for complex digital designs requiring broad language and verification-methodology support.
Hardware-assisted simulation and emulation
HES-DVM
HES-DVM is a hardware-assisted verification solution designed to accelerate HDL simulation, support full-design emulation, and enable hardware/software co-simulation. It is intended for embedded-system and digital-hardware projects where software-only simulation may not provide sufficient speed or capacity.
Linting and clock-domain-crossing verification · 2015
ALINT-PRO
ALINT-PRO provides a framework for design-rule checking, HDL linting, and clock-domain-crossing analysis. It can inspect Verilog, VHDL, and SystemVerilog sources and perform checks across complete design hierarchies. Its configurable rule sets and API are intended to support both predefined and organization-specific verification practices across multiple FPGA implementation technologies.
Requirements lifecycle management · 2013
Spec-TRACER
Spec-TRACER is a requirements lifecycle management application tailored to FPGA and ASIC development. It supports requirements capture, organization, analysis, traceability, and reporting, and is designed to connect requirements work with HDL design and simulation workflows.
FPGA-based ASIC prototyping system · 2012
HES-7
HES-7 is a high-capacity FPGA-based ASIC prototyping platform. Based on Xilinx Virtex-7 technology, it is designed to allow engineers to test and prototype large ASIC designs in hardware, supporting designs described in the source material as reaching up to 24 million ASIC gates.
Embedded SoC FPGA development hardware · 2016
TySOM
TySOM is a line of embedded-development boards and FMC daughter cards based on Xilinx Zynq-7000 SoC FPGA technology. The platform is aimed at embedded applications including IoT, advanced driver-assistance systems, and industrial machine vision.
FPGA compliance and verification system
DO-254 Compliance Test System
The DO-254 Compliance Test System is a specialized verification solution intended to support FPGA compliance work under the DO-254/ED-80 aerospace hardware guidance. It uses in-hardware simulation and can reuse simulation testbenches and coverage information to connect RTL verification with target-device testing and requirements traceability.
Brand decisions
2016
Broaden into embedded SoC FPGA developmentStrategyBackground
The growth of programmable SoC platforms created opportunities for development hardware beyond conventional FPGA design tools.
Action taken
Aldec introduced the TySOM product line of SoC FPGA development boards and expansion hardware.
Aftermath
TySOM extended Aldec’s offering toward embedded applications such as IoT, automotive assistance systems, and industrial vision.
2012
Enter high-capacity SoC and ASIC prototypingStrategyBackground
Engineering teams needed to validate larger ASIC and SoC designs in hardware before production implementation.
Action taken
Aldec introduced HES-7, an FPGA-based ASIC prototyping solution.
Aftermath
The product broadened Aldec’s role from HDL simulation and analysis into larger-scale hardware prototyping.
2001
Expand from simulation software into hardware-assisted verificationStrategyBackground
Large and increasingly complex digital designs created pressure to improve simulation speed and to test designs closer to their eventual hardware environment.
Action taken
Aldec added the HES hardware simulation platform for acceleration, emulation, and incremental prototyping.
Aftermath
The move established hardware-assisted verification and prototyping as a continuing part of Aldec’s portfolio, later including HES-7 and related solutions.
1997
Shift toward HDL-centered FPGA developmentStrategyBackground
The increasing use of VHDL and Verilog created demand for development environments organized around hardware description languages rather than only schematic and netlist entry.
Action taken
Aldec launched Active-VHDL and subsequently added Verilog support, renaming the broader product Active-HDL.
Aftermath
Active-HDL became the company’s principal integrated FPGA design and verification environment and remained part of its portfolio in later years.
Recent events
- 2020
Aldec adds VHDL-2019 support[1]
Product generation
The company reported support for the IEEE 1076-2019 revision of VHDL.
- 2016
Aldec launches the TySOM embedded development product line[1]
Product launch
TySOM extended Aldec into embedded development using SoC FPGA technology, including boards and FMC daughter cards.
- 2015
Aldec introduces ALINT-PRO with CDC verification[1]
Product launch · Product generation
ALINT-PRO combined linting, design-rule checking, and clock-domain-crossing analysis in a broader verification framework.
- 2013
Aldec releases Spec-TRACER[1]
Product launch
Spec-TRACER introduced requirements lifecycle management and traceability functions tailored to FPGA and ASIC development.
- 2012
Aldec enters SoC and ASIC prototyping with HES-7[1]
Product launch
HES-7 expanded Aldec’s hardware portfolio into high-capacity FPGA-based ASIC prototyping.
- 2011
Aldec delivers verification-methodology support and a design emulator[1]
Product launch · Product generation
The company reported support for UVM, OVM, and VMM and released a 4 MHz design emulator.
- 2010
Aldec adds VHDL-2008 support[1]
Product generation
Aldec tools added support for the IEEE 1076-2008 revision of the VHDL standard.
- 2008
Aldec introduces ALINT design-rule checking[1]
Product launch
The company released ALINT, a configurable design-rule-checking and linting product based on rules associated with the STARC consortium.
- 2006
Riviera-PRO supports the Open IP Encryption Initiative[1]
Product generation · Other
Aldec stated that Riviera-PRO supported the Open IP Encryption Initiative associated with Synplicity.
- 2005
Aldec tools add MATLAB and Simulink interfaces[1]
Product generation
Integration with MATLAB and Simulink extended Aldec’s tools into model-based and mixed engineering workflows.
Showing the 10 most recent.
Sources1 sources
Cite this profile: Cite the canonical profile. /brand-wiki/aldec · Editorial policy · How profiles are compiled