Sasikanth Manipatruni — BrandWiki

Sasikanth Manipatruni

Overview

Sasikanth Manipatruni

birth date	1984 (age 42)
workplaces	Intel General Electric Research Laboratory Cornell University ETH Zurich Indian Institute of Science Inter-University Centre for Astronomy and Astrophysics
alma mater	Cornell University ETH Zurich IIT Delhi Indian Institute of Science Jawahar Navodaya Vidyalaya
thesis title	Scaling silicon nanophotonic interconnects : silicon electrooptic modulators, slowlight & optomechanical devices
thesis url	https://cornell.on.worldcat.org/oclc/671537607
thesis year	2010
doctoral advisor	Michal Lipson Alexander Gaeta
academic advisors	Ajoy Ghatak Manfred Morari Christopher J. Hardy Keren Bergman

Sasikanth Manipatruni is an Indian-American computer scientist and inventor known for his work in Beyond CMOS energy-efficient computing, spintronics and Silicon photonics. He is the lead author on Intel's 2018 Nature paper proposing MESO magneto-electric spin-orbit devices, an experimental beyond-CMOS logic technology combining Multiferroics and spin-orbit coupling to achieve ultra-low switching energies. His research has been covered by independent science outlets including Berkeley News,[5] Physics World,[6] Nature research communities[7] and The Register[8][9] and expert peer reviewed research reviews in Nature,[10] Reviews of Modern Physics,

Selected publications and patents

Manipatruni, Sasikanth; Nikonov, Dmitri E.; Lin, Chia-Ching; Gosavi, Tanay A.; Liu, Huichu; Prasad, Bhagwati; Huang, Yen-Lin; Bonturim, Everton; Ramamoorthy Ramesh; Young, Ian A. (2018-12-03). "Scalable energy-efficient magnetoelectric spin–orbit logic". Nature. 565 (7737): 35–42. doi:10.1038/s41586-018-0770-2. ISSN 0028-0836
Manipatruni, S., Nikonov, D.E. and Young, I.A., 2018. Beyond CMOS computing with spin and polarization. Nature Physics, 14(4), pp. 338–343
Manipatruni, S., Nikonov, D.E. and Young, I.A., 2014. Energy-delay performance of giant spin Hall effect switching for dense magnetic memory. Applied Physics Express, 7(10), p. 103001.
Manipatruni, S., Nikonov, D.E. and Young, I.A., 2012. Modeling and design of spintronic integrated circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(12), pp. 2801–2814.
Pham, V.T., Groen, I., Manipatruni, S., Choi, W.Y., Nikonov, D.E., Sagasta, E., Lin, C.C., Gosavi, T.A., Marty, A., Hueso, L.E. and Young, I.A., 2020. Spin–orbit magnetic state readout in scaled ferromagnetic/heavy metal nanostructures. Nature Electronics, 3(6), pp. 309–315.
Chen, Z., Chen, Z., Kuo, C.Y., Tang, Y., Dedon, L.R., Li, Q., Zhang, L., Klewe, C., Huang, Y.L., Prasad, B. and Farhan, A., 2018. Complex strain evolution of polar and magnetic order in multiferroic BiFeO3 thin films. Nature communications, 9(1), pp. 1–9.
Xu, Q., Manipatruni, S., Schmidt, B., Shakya, J. and Lipson, M., 2007. 12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators. Optics express, 15(2), pp. 430–436.
Manipatruni, S., Nikonov, D.E., Lin, C.C., Prasad, B., Huang, Y.L., Damodaran, A.R., Chen, Z., Ramesh, R. and Young, I.A., 2018. Voltage control of unidirectional anisotropy in ferromagnet-multiferroic system. Science advances, 4(11), p.eaat4229.
Zhang, M., Wiederhecker, G.S., Manipatruni, S., Barnard, A., McEuen, P. and Lipson, M., 2012. Synchronization of micromechanical oscillators using light. Physical review letters, 109(23), p. 233906.
Manipatruni, S., Robinson, J.T. and Lipson, M., 2009. Optical nonreciprocity in optomechanical structures. Physical review letters, 102(21), p. 213903.
Fang, M.Y.S., Manipatruni, S., Wierzynski, C., Khosrowshahi, A. and DeWeese, M.R., 2019. Design of optical neural networks with component imprecisions. Optics Express, 27(10), pp. 14009–14029.
Chen, L., Preston, K., Manipatruni, S. and Lipson, M., 2009. Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors. Optics express, 17(17), pp. 15248–15256.
Dutt, A., Luke, K., Manipatruni, S., Gaeta, A.L., Nussenzveig, P. and Lipson, M., 2015. On-chip optical squeezing. Physical Review Applied, 3(4), p. 044005.

AI and in-memory computing

Korgaonkar, K., Bhati, I., Liu, H., Gaur, J., Manipatruni, S., Subramoney, S., Karnik, T., Swanson, S., Young, I. and Wang, H., 2018, June. Density tradeoffs of non-volatile memory as a replacement for SRAM based last level cache. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) (pp. 315–327). IEEE.
Pipeline circuit architecture to provide in-memory computation functionality, US20190057050A1 [127]
Low synch dedicated accelerator with in-memory computation capability, US20190056885A1 [128]
In-memory analog neural cache, US20190057304A1,[129]

Computational logic devices and quantum materials

In 2016, Manipatruni and collaborators proposed a number of changes to the new logic device development by identifying the core criterion for the logic devices for utilization beyond the 2 nm process.[25] The continued slow down the Moore's law as evidenced by slow down of the voltage scaling,[119][120] lithographic node scaling and increasing cost per wafer and complexity of the fabs indicated that Moore's law as it existed in the 2000-2010 era has changed to a less aggressive scaling paradigm.

Manipatruni proposed [25] that spintronic and multiferroic systems are leading candidates for achieving attojoule-class logic gates for computing, thereby enabling the continuation of Moore's law for transistor scaling. However, shifting the materials focus of computing towards oxides and topological materials requires a holistic approach addressing energy, stochasticity and complexity.

The Manipatruni-Nikonov-Young Figure-of-Merit for computational quantum materials is defined as the ratio of " energy to switch a device at room temperature" to " energy of thermodynamic stability of the materials compared to vacuum energy, where \pm\theta is the reversal of the order parameter such as ferro-electric polarization or magnetization of the material"

This ratio is universally optimal for a ferro-electric material and compared favorably to spintronic and CMOS switching elements such as MOS transistors and BJTs. The framework (adopted by SIA decadal plan[121]) describes a unified computing framework that uses physical scaling (physics-based improvement in device energy and density), mathematical scaling (using information theoretic improvements to allow higher error rate as devices scale to thermodynamic limits) and complexity scaling (architectural scaling that moves from distinct memory & logic units to AI based architectures). Combining Shannon inspired computing allows the physical stochastic errors inherent in highly scaled devices to be mitigated by information theoretic techniques.[122][123]

Ian A. Young, Nikonov, and Manipatruni have provided a list of 10 outstanding problems in quantum materials as they pertain to computational devices. These problems have been subsequently addressed in numerous research works leading to various improved device properties for a future computer technology Beyond CMOS. The top problems listed as milestones and challenges for logic are as follows:

Problems of magnetic/ferro-electric/multiferroic switching

Magneto-electric spin-orbit logic is a design using this methodology for a new logical component that couples magneto-electric effect and spin orbit effects. Compared to CMOS, MESO circuits could potentially require less energy for switching, lower operating voltage, and a higher integration density.[26]

1) How to switch a magnetic/multiferroic (MF) state in volume of 1,000 nm3 with a stability of 100 kBT and an energy of 1 aJ ~ 6.25 eV ~ 240 kT?
2) What are the timescales involved with magnetoelectric/ferroelectric (FE)/MF switching of a magnet/FE/MF at scaled sizes? How to overcome the Larmor precession timescale of a ferromagnet?
3) How to switch a scaled magnet/polarization switch with low stochastic errors? What are the fundamental mechanisms governing the switching errors, fatigue for scaled FE/ME switching?
4) What is the right combination of materials/order parameters for practical magnetoelectric switching (for example, multiferroic FE/antiferromagnet (AFM) plus FM, paraelectric/AFM plus FM, piezoelectric plus magnetostriction)? Problems of magnetic/multiferroic/ferroelectric detection
5) How to detect the state of a magnet/ferroelectric with high read-out voltage >100 mV? For inverse spin–orbit effects, such as the spin galvanic effect/Edelstein effect, how to achieve λIREE > 10 nm with high resistivity?
6) What is the scaling dependence of spin–orbit detection of the state of a magnet? How to detect the state of a perpendicular magnet with spin–orbit effect? Problems of interconnects and complexity
7) How to transfer the state of a magnet/FE over long distances on scaled wire sizes (<30-nm-wide wires with pitch <60 nm)? In particular, how to improve the spin diffusion interconnects in non-magnetic conductors and magnon interconnects in magnetic interconnects?
8) How to transduce a spintronic/multiferroic state to a photonic state (and vice versa) to enable very long-distance interconnects (>100 μm)67?
9) The back-end of CMOS comprises multiple layers of metal wires separated by a dielectric. Tus making logic devices between these layers requires starting with an amorphous layer and a template for growth of the functional materials. How to integrate the magnetic/FE/MF materials in the back-end of the CMOS chip50,68?