Centaur Technology

Centaur Technology was an x86 CPU design company started in 1995 and subsequently a wholly owned subsidiary of VIA Technologies. In 2015, the documentary Rise of the Centaur covered the early history of the company.[1] The company was broken up in 2021.[2]

History

Centaur Technologies Inc. was founded in April 1995 by Glenn Henry, Terry Parks, Darius Gaskins, and Al Sato. The funding was provided by Integrated Device Technology, Inc (IDT). The business goal was to develop compatible x86 processors that were less expensive than Intel processors and consumed less power. There were two main elements of the plan:

While funded by IDT, three different Centaur designs were shipped under the marketing name of WinChip. In September 1999, Centaur was purchased from IDT by VIA Technologies

Design methodology

Centaur's chips historically have been much smaller than comparable x86 designs at their time, and they are thus cheaper to manufacture and consume less power. This made them attractive in the embedded marketplace.

Centaur's design philosophy was always centered on "sufficient" performance for tasks that its target market demands. Some of the design trade-offs made by the design team ran contrary to accepted wisdom.

Centaur/VIA was among the first to design processors with hardware encryption, hash and random number acceleration in the form of VIA PadLock, starting with a 2004 VIA C7 release. Around the same time NSC Geode LX added support for AES128. In 2008 Intel and AMD followed up with specifications AES-NI, Intel SHA extensions in 2013, and RDRAND in 2015.

VIA C3

Because memory performance is the limiting factor in many benchmarks, VIA processors implement large primary caches, large TLBs, and aggressive prefetching, among other enhancements. While these features are not unique to VIA, memory access optimization is one area where features were not sacrificed to save die space. In fact, generous primary caches (128KB) have always been a distinctive hallmark of Centaur designs.
Generally, clock frequency is favored over increasing instructions per cycle. Complex features such as out-of-order instruction execution are deliberately not implemented, because they impact the ability to increase the clock rate, require a lot of extra die space and power, and have little impact on performance in several common application scenarios.
The pipeline is arranged to provide one-clock execution of the heavily used register–memory and memory–register forms of x86 instructions. Several frequently used instructions require fewer clock cycles than on other x86 processors.
Rarely used x86 instructions are implemented in microcode and emulated as combinations of other x86 instructions. This saves die space and contributes to low power consumption. The impact on the majority of real-world application scenarios is minimal.
These design principles are derivative from the original RISC advocates, who claim that a smaller set of instructions, better optimized, can deliver faster overall CPU performance. The C3 design cannot be considered a pure RISC design because it accepts the x86 instruction set which is a CISC design.
In addition to x86, these processors support the undocumented Alternate Instruction Set.

VIA C7

VIA C7 Esther (C5J) as an evolutionary step after VIA C3 Nehemiah+ (C5P), in which Centaur followed its traditional approach of balancing performance against a constrained transistor/power budget.
The cornerstone of the VIA C3 series chips' design philosophy has been that even a relatively simple in-order scalar core can offer reasonable performance against a complex superscalar out-of-order core if supported by an efficient "front-end", i.e. prefetch, cache and branch prediction mechanisms.
In the case of VIA C7, the design team focused on further streamlining the "front-end" of the chip, i.e. cache size, associativity and throughput as well as the prefetch system.[6] At the same time, no significant changes to the execution core ("back-end") of the chip seem to have been made.
The VIA C7 successfully further closes the gap in performance with AMD/Intel chips, since clock speed is not thermally constrained.

VIA Nano

VIA Nano Isaiah (CN) is a combination of a number of firsts from Centaur, including its first superscalar out-of-order CPU and its first 64-bit CPU.
The development of the VIA Nano focused on radically improving the performance side of the performance-per-watt equation while still maintaining a similar TDP to the VIA C7.

CNS core

Centaur announced a new x86-64 "CNS" CPU with AVX-512 support and integrated AI coprocessor in late 2019.[7] The CNS CPU was cancelled in 2021 when VIA sold parts of its Centaur division to Intel.[3] The CNS core CPUs had up to 8 cores and ran at a 2 GHz base frequency. It used the same LGA2011 pin socket as Intel's LGA2011-3 CPUs, however it is not electrically compatible with Intel motherboards. The CNS CPU cores were made on the TSMC 16 nm node. Some of the advancements made on CNS were later used in some CLUs by Zhaoxin Semiconductor, which is a joint venture co-owned by VIA.[8]

The CHA SoC comprised eight CNS cores and a 4096-wide deep learning coprocessor referred to as Ncore[9]. The deep learning accelerator was evaluated on the MLPerf Inference v0.5 benchmark[10]. Of its several results in that public benchmark submission, its MobileNetv1 Stream result was notable for being the lowest latency result among all systems benchmarked from all closed-division entrants.

Comparative die size

Note: Even the 180 nm Duron Morgan core (106 mm²) with a 64K secondary cache, when shrunk down to a 130 nm process, would have still had a die size of 76 mm². The VIA x86 core is smaller and cheaper to produce. As can be seen in this table, almost four C7 cores could be manufactured in the same area as a one-P4 Prescott core on 90 nm process.

type	Incorporated
industry	Electronics
founded	April 1995 in Austin, United States
founders	Glenn Henry, Terry Parks, Darius Gaskins, and Al Sato
defunct	November 2021
fate	Broken up, partially acquired by Intel
hq location city	Austin, Texas
hq location country	United States
key people	Glenn Henry
products	x86 CPU designs
owner	VIA Technologies